Circuit arrangement having a dual coil for producing an alternating voltage or an alternating current

ABSTRACT

The invention relates to a circuit arrangement for producing an alternating voltage or an alternating current from a unipolar direct current source having an inverter relating to a neutral conductor. The direct current source is connected to an inverter which converts the unipolar voltage of the direct current source into a bipolar intermediate circuit voltage that is stored in a buffer circuit (C 1 , C 2 ) which is connected to the inverter. The inverter comprises a clocked switch (S o ) and an energy converting unit which is configured as a dual coil (DR 1 ,DR 2 ) having two windings (W 1 ,W 2 ) which are closely coupled to each other.

The invention relates to a circuit arrangement for producing an alternating voltage or an alternating current according to the preamble of the main claim.

A large number of circuit arrangements for producing an alternating (AC) voltage or an alternating (AC) current from a unipolar direct (DC) voltage source is known, a differentiation being made in the case of these inverters between inverters without galvanic separation, i.e. transformerless inverters, and those with galvanic separation, i.e. transformer inverters.

The highest efficiency is achieved with transformerless inverters in a full-bridge circuit without step-up converters. In the case of these circuits, the potential of the source with mains frequency and half mains voltage oscillates relative to earth potential. Hence a restriction exists in the applicability of these concepts in the case of sources with a high stray or leakage capacitance relative to earth potential, as is the case for example with solar generators of specific technology, in particular thin-film modules.

Furthermore, transformerless concepts are known, e.g. from DE 196 42 522 C1 and DE 197 32 218 C1, in which one terminal of the solar generator is connected rigidly to the neutral conductor and hence has a fixed potential relative to earth potential. In the case of these known circuit arrangements, also in the case of any high leakage capacitances, in principle no leakage currents can flow. In the case of these single phase supplying inverters, a buffer capacitor is required which is located at the input of the inverter and must cover the entire input voltage range. This design is therefore not optimal and is expensive. In addition, the mentioned concepts are distinguished by high complexity and poor efficiency.

US 2004/0 164 557 describes a solar inverter in which the solar generator is connected, on the one side, to the neutral connector of the mains and supplies an intermediate circuit with two capacitors which serve for buffering, which is configured to be bipolar relative to the neutral conductor. Since the output voltage of the solar generator actually forms the positive intermediate circuit voltage relative to the potential of the neutral conductor, for example with 230 V effective (RMS) mains voltage, only solar generator voltages greater than 350 V can be used, which in practice represents a considerable restriction.

The object therefore underlying the invention is to produce a circuit arrangement for producing an alternating voltage or an alternating current from a grounded, unipolar voltage, i.e. a direct voltage source which is connected rigidly to the neutral conductor, which offers high efficiency, which is based on simple, economical, reliable structures which are easily controllable with respect to control technology, and permits an input voltage range both below and above the mains voltage amplitude (typically 325 V with an effective value of 230 V).

This object is achieved according to the invention by the characterising features of the main claim in conjunction with the features of the preamble.

Advantageous developments and improvements are possible as a result of the measures indicated in the sub-claims.

The concept comprises a converter stage which converts the input voltage, i.e. the voltage made available by a direct voltage source, such as for example a solar generator, into a bipolar intermediate circuit voltage of e.g. +/−350 V which is stored in capacitors, and an inverter which produces an alternating current from this bipolar intermediate circuit voltage which can be supplied then into the mains. The direct voltage source, i.e. the solar generator, is thereby connected rigidly to the neutral conductor by means of a terminal.

Of advantage in this concept is the decoupling of the input side from the output side via the controlled voltage of the intermediate circuit. Furthermore, the capacitor which is required in the case of a single phase supplying inverter for intermediate storage of energy, in the case of the present invention the two intermediate circuit capacitors, is at a high voltage level which is independent of the input voltage and can be optimised at this voltage level and hence become significantly more economical.

The converter is thereby configured as a choke converter which has a clocked switch and two windings which are disposed closely coupled to each other, and which, in contrast to the state of the art (DE 196 42 522 C1 and DE 197 32 218 C1), need to be designed only for the nominal power of the inverter since energy can be stored in the voltage intermediate circuit and not to the power which is twice as high when occurring at the maximum of the output current.

A further advantage of this concept resides in the fact that the input voltage can be both smaller and greater in value than the voltage of the intermediate circuit capacitors and hence energy sources with a wide voltage range can be connected.

The configuration according to the invention has the advantage in addition that a recovery path via the assigned recovery diodes into the high-capacitance intermediate circuit capacitors is always inherently present for the energy stored in the dual coil. This is required for safe shut down in all operating states (emergency cut-off).

It is particularly advantageous that the windings of the dual coil are connected such that some of the respectively assigned winding ends are at rest potential (neutral conductor or intermediate circuit capacitor) and the others of the respectively assigned winding ends have the same voltage course offset by the value of the intermediate circuit voltage, and consequently no cyclic recharging of the coupling capacitances between the windings is required, as a result of which smaller peak currents occur at the switch S₀ and the efficiency and also the EMC behaviour are improved.

It is advantageous that the windings of the converter coil which is termed dual coil have the same numbers of turns and are configured closely coupled to each other since the same voltage is consequently induced in both so that, in the ideal case, the two buffer capacitors or also intermediate circuit capacitors are charged to the same voltage without balancing measures. By further provision of a capacitor C₃ between the winding ends with the same temporal voltage course, the energy stored in the unavoidable leakage inductances of the dual coil can be absorbed when opening the switch S₀ and in the next cycle portion are transmitted almost loss-free to the intermediate circuit.

In another advantageous embodiment, a limiting circuit is provided for limiting the voltage at the second winding of the dual coil during connection of the clocked switch, which has a coupling capacitor connected to the second winding and diodes connected to it. The limiting circuit prevents, in the interaction of the coupling capacitor with the diodes, occurrence of damaging high voltages via the recovery diode assigned to the second winding due to transient phenomena at the second winding when switching on the clocked switch. In this embodiment, the windings are designed differently with respect to their turns, i.e. the second winding has more turns, as a result of which the coupling capacitor can be kept small.

Advantageously, the obtained bipolar intermediate circuit voltage is converted via the subsequently connected inverter which is known per se into a mains-conforming alternating current.

By using an inverter in the form of a three-point circuit, which is known per se, or of an inverter with additional recovery paths, improved efficiency and improved EMC behaviour can be achieved by reducing the current ripple.

The circuit arrangement according to the invention can be configured also to be multiphase, e.g. three-phase, for supplying into the normal public three-phase mains.

Furthermore, the invention is not restricted to a solar generator as direct voltage source, also fuel cells, batteries or the like can be used.

Embodiments of the invention are represented in the drawing and are explained in more detail in the subsequent description. There are shown:

FIG. 1 a first circuit-type configuration of the invention,

FIG. 2 a second circuit-type configuration of the invention,

FIG. 3 a third circuit-type configuration of the invention,

FIG. 4 a fourth circuit-type configuration of the invention,

FIG. 5 a fifth circuit-type configuration of the invention, and

FIG. 6 a sixth circuit-type configuration of the invention.

The circuit arrangement represented in FIG. 1 has a direct voltage source which, in the embodiment, is a solar generator 1 which is located with the terminals thereof on a positive line 2 and on a neutral or earth conductor 3. This solar generator 1 delivers an input direct voltage U_(SG). A capacitor C₀ which buffers the input voltage U_(SG) is provided parallel to the solar generator 1. Between the lines 2, 3, there is located the series circuit of a first winding W₁ of a coil which is termed dual coil DR₁, and of a switch S₀ which is clocked by a control unit, not represented, and which can be configured as a transistor, preferably as a MOS-FET or as an IGBT. The points on the windings W₁, W₂ characterise the winding starts thereof in the known manner. The second winding W₂ of the dual coil DR₁ is connected by the winding start to the neutral conductor 3, the winding end being connected to a first recovery diode D₁ which is connected by its other terminal to a first storage capacitor C₁, the other terminal of which is located on the neutral conductor 3. At the connection point between first winding W₁ and the switch S₀, a second recovery diode D₂ is connected, the second terminal of which is connected to a second storage capacitor C₂, the second terminal of which is likewise located on the neutral conductor 3.

The dual coil represents a transformer with energy storing properties, the galvanic separation of which is however not used in the present case. The winding W₁ is used doubly for supplying energy and for producing a voltage inverted relative to the potential of the neutral conductor 3. The winding W₂ serves to produce a voltage with the same polarity as the input voltage relative to the neutral conductor. It is advantageous that the two intermediate circuit voltages +/−U_(WR) can be both smaller and greater in value than the prescribed input voltage U_(SG). The windings W₁ and W₂ advantageously have the same number of turns and are wound on a core closely coupled to each other, said windings also being able to be wound in a bifilar manner. The buffered input voltage U_(SG) is applied via the switch S₀, which is clocked for example with 16 kHz, to the first winding W₁ of the dual coil DR₁, as a result of which, in the first clock phase in which the switch S₀ is connected through, a temporally increasing current is built up in the winding W₁, connected to an energy store in the magnetic circuit of the dual coil DR₁. In the second clock phase, the switch S₀ is opened and, in the two windings W₁ and W₂ of the dual coil DR₁, a recovery voltage is induced in such a manner that a charging current flows via the diode D₁ into the capacitor C₁ and at the same time a charging current flows via the diode D₂ into the capacitor C₂. Because of the equal number of turns of both windings W₁ and W₂ and their close coupling, the same voltage is induced in both so that, according to the charging processes, finally the two capacitors C₁, C₂ are charged without further balancing measures almost to the same voltage, e.g. 350 V. At the terminals of the storage capacitors C₁ and C₂ which are connected to the recovery diodes D₁ and D₂, a bipolar intermediate circuit voltage +/−U_(WR) occurs, which supplies a subsequently connected inverter which is configured, in the represented case, as a half-bridge with the switches S₁ and S₂, the connection point of which is connected to a supply coil L₁. The other terminal of the supply coil L₁ is connected to one of the phases L of the mains 4 into which an alternating current is intended to be supplied, the mains voltage being termed U_(mains).

The switches S₁ and S₂ of the half-bridge circuit are actuated in a manner known per se according to a specific clock pattern (e.g. pulse width modulation, PWM) by a control circuit, not represented, and a mains supply can be undertaken via the supply coil L₁. Hence, the bipolar intermediate circuit voltage +/−U_(WR) obtained as described above can be converted via the subsequently connected inverter into a mains-conforming alternating current.

A further embodiment of the circuit arrangement according to the invention of an inverter with a voltage intermediate circuit is represented in FIG. 2. The circuit differs from the circuit arrangement according to FIG. 1 in that a so-called three-level circuit is used as inverter and comprises respectively two switches S₁, S₃ and S₂, S₄ which are connected in series, a recovery diode D₃ being connected between the connection point of the switches S₁ and S₃, said recovery diode being located with its second terminal on the neutral conductor 3, whilst the connection point between the switches S₄ and S₂ is connected via a recovery diode D₄ to the neutral conductor 3. The supply coil L₁ is located with its one terminal at the connection point between the switches S₃ and S₄.

The half-bridge circuit according to FIG. 1, with alternately closed switches S₁, S₂, allows only the two voltage levels +U_(WR) and −U_(WR) at the input of the coil L₁. The three-level circuit according to FIG. 2 allows, on the other hand, three switching states. In the positive half-wave, S₃ is permanently closed, S₁ is clocked with e.g. 16 kHz and the switches S₂ and S₄ remain open. When the switch S₁ is closed, the voltage +U_(WR) occurs at the input of the coil L₁ and a current is built up. After opening S₁, the current flows further via the diode D₃ and the closed switch S₃. In the case of ideal components, the voltage drop over them would be zero volts, correspondingly also the input voltage at the coil L₁. Hence the latter is demagnetised substantially more slowly relative to the circuit according to FIG. 1, which has a positive effect on efficiency and the EMC behaviour. In the negative half-wave, the switches S₂ and S₄ are correspondingly used.

The represented inverter circuit has the advantage in addition that semiconductors with a lower electric strength and hence better electrical properties can be used. However it is disadvantageous that the current must always flow through at least two semiconductors.

A further advantageous embodiment of a circuit arrangement is represented in FIG. 3, said circuit arrangement comprising, like that in FIG. 1, a half-bridge with the switches S₁ and S₂ and also the subsequently connected coil L₁, but differs in that additional recovery branches between the connection point between the switches S₁ and S₂ and the neutral conductor 3 are provided, which comprise a switch S₃ and a diode D₃ and a diode D₄ and a switch S₄. Like that according to FIG. 2, this circuit also allows three switching states with the indicated advantages. The same function of the additional recovery path is fulfilled here by the switches S₃, S₄, together with the diodes D₃, D₄. In the positive half-wave, S₃ is permanently closed, correspondingly S₄ in the negative one. The advantage relative to the circuit according to FIG. 2 resides in the fact that in the build-up phase of the current, in which for example switch S₁ is closed, the current need flow only through one switch, i.e. S₁, as a result of which the efficiency is increased relative to the circuit according to FIG. 2.

A connection between the two recovery paths is represented in broken lines in FIG. 3. In the connected case, so-called co-packs are used as electronic switches, in the case of which an IGBT, for example switch S₃, is wired to a recovery diode, e.g. diode D₄, in a common housing. With two such commercially available components, the desired switch/diode combination can then be constructed. The same arrangement is produced if MOS-FETs are used as switches—the body diodes inherently present with MOS-FETs take over the function of the recovery diodes.

In FIG. 4 and FIG. 5, further embodiments are represented which are particularly preferred circuits.

FIG. 4 differs from the embodiment according to FIG. 3 in that the sequence within the series circuit of the winding W₂ of the dual coil DR₁ and the recovery diode D₁ is exchanged. This means that the recovery diode D₁ is connected by its one terminal to the neutral conductor 3 and, by its other terminal, to the winding start of the winding W₂, the other terminal of which is connected to the capacitor C₁. In addition, a capacitor C₃ is connected respectively to the winding start of the winding W₁ and to the winding start of the winding W₂. Basically, the functional mode is as described previously, i.e. the general function remains unchanged. However, it is of advantage that both winding ends of the windings W₁, W₂ are at rest potential, i.e. at the reference potential, which is prescribed by the neutral conductor 3, or at the intermediate circuit voltage +U_(WR) applied to the intermediate circuit capacitor C₁. The two winding starts have thus the same temporal voltage course relative to each other, offset by the level of the intermediate circuit voltage +U_(WR). Hence, the two windings W₁, W₂ can be wound very closely adjacent to each other, for example as a bifilar winding, since the parasitic coupling capacitance forming between the two windings need not have a charge reversal at each cycle. From the spatially narrow construction there results a very good magnetic coupling of the windings W₁, W₂ and hence a low leakage inductance, an improved EMC behaviour and also lower switching losses in the switch S₀.

Since in the circuit according to FIG. 4 the two winding starts ideally have the same voltage course but offset by the value of the output voltage U_(WR), the two winding starts can be connected to the capacitor C₃. This additional capacitor C₃, when switching off the switch S₀, absorbs a part of the energy stored in the primary-side leakage inductance of the dual coil DR₁ and emits this in the next cycle via the winding W₂ to the output +U_(WR). As a result, excess voltages are limited during the switching process and further balancing of the output voltages is achieved.

In the circuit according to FIG. 4, the coupling capacitor C₃ has, as mentioned, the task of absorbing the energies stored in the leakage inductances and ensuring equalisation between the two intermediate circuits. However, the capacitor must be designed to be relatively large for this purpose, e.g. several 100 μF in the case of a 5 kW appliance. A compromise with respect to a smaller capacitor would reside in making the numbers of turns of the windings W₁ and W₂ not exactly equal but in giving the winding W₂ a somewhat higher number of turns. Hence, in the case of small powers, the voltage at the intermediate circuit capacitor C₁ would be slightly excessive, in the case of average powers, both would correspond well and, with full power, the negative intermediate circuit capacitor C₂ would be supplied in addition from the leakage inductance of the first winding W₁ so that its voltage would be slightly above that of C₁. With such a solution, a clock-frequency alternating voltage however then occurs at the coupling capacitor C₃, associated with undesired currents through C₃ and through all surrounding components.

In FIG. 5, the mentioned problem is taken into account. Furthermore, a coupling capacitor C₃ is connected between the second winding W₂ and assigned recovery diode D₁, the other terminal of C₃ being connected to a first and second diode D₆ and D₇. D₇ is located with its other terminal at the negative intermediate circuit voltage −U_(WR) and D₆ is connected to a further capacitor C₄ which is applied at the positive line 2 or at the corresponding terminal of the clocked switch S₀. At the connection point between C₄ and first diode D₆, a third diode D₅ is connected, said third diode being located with its cathode at the connection point between the switch S₀ and the first winding W₁. Parallel to the switch S₀, a recovery diode D₀, which can also be present in the other embodiments, is provided.

In order that the coupling capacitor C₃ can be kept small (e.g. C₃=100 nF), the windings, as mentioned above, are designed differently (W₂ has more turns) so that the voltage differences of the intermediate circuits remain tolerable both with a small load and with a large load. Capacitor C₃ no longer has the task (see FIG. 4) of holding the two intermediate circuit capacitors together with respect to voltage. Rather, it prevents, in the interaction with the diodes D₅, D₆, D₇, the occurrence of damagingly high voltages across the diode D₁ due to transient phenomena at the winding W₂ when switching on the switch S₀.

The coupling capacitor C₃ is charged on average to the positive intermediate circuit voltage +U_(WR). When the switch S₀ is closed, the start of the winding W₂ is at the voltage (U_(SG)+U_(WR)). If spikes occur, then the diodes D₀, D₅ and D₆ become conductive and delimit the voltage at the second winding W₂.

If only this fundamentally important limiting function is intended to be produced, then the third diode D₅ and the capacitor C₄ can be dispensed with.

With the diode D₅ and the capacitor C₄, additional relief of the switch S₀ when switching off is achieved.

The initial situation may be a closed circuit S₀ and a discharged capacitor C₄. If now the switch opens, then the inductance of the dual coil attempts to maintain the current flow. Since the switch does not open ideally rapidly (in particular IGBTs), current and voltage occur at the same time in the switch for a certain time, which leads to the thus mentioned switching losses. These can be reduced if a switch relieving is provided, here in the form of the capacitor C₄. As soon as the voltage across the switch increases, the capacitor C₄ is charged via the diode D₅—the coil current therefore flows in the ideal case completely through D₅ and C₄ and the switch is relieved. At the end of the cut-off process, the capacitor C₄ is charged to the sum of the input voltage U_(SG) and the negative intermediate circuit voltage −U_(WR). The next time the switch S₀ is switched on, the energy stored in the capacitor C₄ is supplied back to the input circuit again almost loss-free in that, via the second winding W₂, the coupling capacitor C₃ and also the first diode D₆, a charge reversal current flows until the capacitor C₄ is again completely discharged. Further charge reversal is prevented via the diodes D₅ and D₀. In order that the charge reversal functions as described, C₃>>C₄ should be chosen, which however is provided anyway because of the double function of C₃.

The circuits according to FIGS. 1 to 5 can also have a complementary construction. FIG. 6 shows by way of example the complementary construction of the circuit according to FIG. 4.

In FIG. 6, the positive terminal of the direct voltage source 1, i.e. of the solar generator, is located on the neutral conductor 3. This has the advantage that all the modules of the solar generator 1 have a negative potential relative to earth potential, which has an advantageous effect on the efficiency thereof with specific types of solar cells. Furthermore, the switch S₀ is located in the negative supply voltage line 6, which simplifies its actuation with respect to circuit technology, in particular if a plurality of parallel-operating input steps is provided. As already mentioned, preferably MOS-FETs or IGBTs of the N-channel type are used as switches. N-channel transistors require a positive gate voltage of e.g. 15 V relative to the emitter potential for actuation, for which purpose an auxiliary voltage must be made available. If a plurality of transistors with their emitters is at the same potential, a common auxiliary voltage source can advantageously be used.

The input stage comprising the capacitor C₀, the switch S₀, the dual coil DR₁, the recovery diodes D₁, D₂ and also the coupling capacitor C₃ can also be provided in multiple form in all the embodiments and supply a common intermediate circuit comprising the intermediate circuit capacitors C₁, C₂.

The individual input stages can be thereby connected to the input terminals connected to the lines 2 and 3 or 3 and 6 and be supplied from the same source.

Advantageously, the associated switches S₀ are thereby clocked in a temporally offset manner so that, both at the input, i.e. at the respective capacitors C₀, and at the output, i.e. at the capacitors C₁, C₂, a comparable power flow is produced, resulting in a lower alternating current loading of these capacitors. Furthermore, a so-called master-slave operation is possible, in which the individual input stages are activated as a function of the power to be transmitted instantaneously. As a result, the efficiency course can be significantly improved, in particular in the partial load range.

If a plurality of input stages is present, then these can also have separate input terminals which in turn can be connected to associated, even different, solar generators or other direct voltage sources.

In the above embodiment, a solar generator is used as direct voltage source. However, also fuel cells or batteries or the like can be provided. 

1. Circuit arrangement for producing an alternating voltage or an alternating current from a direct voltage source which is unipolar relative to a neutral conductor and with an inverter, the direct voltage source (1) being connected to a converter which converts the unipolar voltage of the direct voltage source into a bipolar intermediate circuit voltage which is stored in a buffer circuit connected to the inverter, characterised in that the converter comprises a clocked switch (S₀) and an energy converting unit which is configured as a dual coil (DR₁) having two windings (W₁, W₂) which are disposed closely coupled to each other and is configured in such a manner that the energy delivered via the switch (S₀) is stored intermediately and, therefrom, a voltage inverted relative to the potential of the neutral conductor (3) and a voltage with the same polarity as the unipolar voltage are produced.
 2. Circuit arrangement according to claim 1, characterised in that the buffer circuit has at least two storage capacitors (C₁, C₂) and a recovery diode (D₁, D₂) is assigned to each winding (W₁, W₂) of the dual coil (DR₁), through which recovery diode the respective charging current for the storage capacitors flows.
 3. Circuit arrangement according to claim 1, characterised in that the switch (S₀) is clocked, and in that, in the one switching phase, energy storage takes place in the magnetic circuit of the dual coil (DR₁) and, in the other switching phase, a voltage is induced in both windings in such a manner that the charging current flows into the respective capacitor (C₁, C₂).
 4. Circuit arrangement according to claim 1, characterised in that the series circuit comprising the switch (S₀) and a winding (W₁) of the dual coil (DR₁) is disposed parallel to the direct voltage source.
 5. Circuit arrangement according to claim 1, characterised in that, between the connection point between switch (S₀) and first winding (W₁) and one of the storage capacitors (C₁, C₂) and between the second winding (W₂) and the other of the storage capacitors, respectively one recovery diode (D₁, D₂) is connected, the respectively other terminals of the windings being located on the neutral conductor (3).
 6. Circuit arrangement according to claim 1, characterised in that the windings of the dual coil are connected in such a manner that the terminals of the windings (W₁, W₂) which are termed winding ends are at rest potential and the other terminals which are termed winding starts have the same temporal voltage course.
 7. Circuit arrangement according to claim 6, characterised in that the winding start of the first winding (W₁) is connected via a recovery diode (D₁, D₂) to one of the storage capacitors (C₁, C₂) and one winding end to the neutral conductor, and in that the winding end of the second winding is connected to the other of the storage capacitors (C₁, C₂) and its winding start is connected via the other recovery diode (D₁, D₂) to the neutral conductor (3).
 8. Circuit arrangement according to claim 1, characterised in that the windings (W₁, W₂) of the dual coil (DR₁) have the same numbers of turns.
 9. Circuit arrangement according to claim 6, characterised in that the winding starts of the windings (W₁, W₂) of the dual coil (DR₁) are connected to each other via a coupling capacitor (C₃).
 10. Circuit arrangement according to claim 1, characterised in that the ratio of the numbers of turns of the first (W₁) and of the second winding (W₂) is less than
 1. 11. Circuit arrangement according to claim 1, characterised in that the second winding (W₂) is connected to a limiting circuit for limiting the voltage at the second winding (W₂) during connection of the clocked switch (S₀).
 12. Circuit arrangement according to claim 11, characterised in that the limiting circuit has a coupling capacitor (C₃) connected to the second winding and a first and second diode (D₆, D₇) connected to the other terminal, the second diode (D₇) being at the negative intermediate circuit voltage (−U_(WR)) and the first diode (D₆) being connected to the connection point between the switch (S₀) and the winding (W₁) line (2).
 13. Circuit arrangement according to claim 12, characterised in that a circuit for relieving the clocked switch (S₀) is provided when switching off, said circuit comprising a capacitor (C₄) and a third diode (D₅).
 14. Circuit arrangement according to claim 13, characterised in that the capacitor (C₄) and the third diode (D₅) respectively are connected to the terminals of the clocked switch (S₀) and the connection point between capacitor (C₄) and third diode (D₅) is connected to the first diode.
 15. Circuit arrangement according to claim 1, characterised in that the windings of the dual coil (DR₁) are bifilar windings.
 16. Circuit arrangement according to claim 1, characterised in that the inverter is configured as a half-bridge (S₁, S₂), a supply coil (L₁) being connected between the two switches (S₁, S₂) of the half-bridge.
 17. Circuit arrangement according to claim 1, characterised in that the inverter is configured to be multiphase.
 18. Circuit arrangement according to claim 1, characterised in that, between neutral conductor (3) and connection point between the switches of the inverter which is configured as a half-bridge, two recovery branches (S₃, D₃, S₄, D₄) respectively comprising a switch and a recovery diode are connected.
 19. Circuit arrangement according to claim 1, characterised in that the inverter has two pairs of two electronic switches (S₁, S₃; S₂, S₄) which are connected in series, the connection point of the pairs being connected to a supply coil (L₁) and the connection points of the switches respectively of one pair being connected via recovery diodes to the neutral conductor, a control device controlling the switches respectively of one pair in such a manner that the one switch (S₃, S₄) is closed and the other (S₁, S₂) is clocked.
 20. Circuit arrangement according to claim 1, characterised in that the direct voltage source (1) is a solar generator, a fuel cell and/or a battery.
 21. Circuit arrangement according to claim 1, characterised in that the direct voltage source configured as solar generator is connected by the negative terminal thereof to the neutral conductor and all the modules of the direct voltage source have a positive potential relative to the neutral conductor (3).
 22. Circuit arrangement according to claim 1, characterised in that the direct voltage source configured as solar generator is connected by the positive terminal thereof to the neutral conductor (3) and all the modules of the direct voltage source have a negative potential relative to the neutral conductor (3).
 23. Circuit arrangement according to claim 1, characterised in that a plurality of input stages comprising electronic switch (S₀), double coil (DR₁) and assigned recovery diodes (D₁, D₂) and possibly coupling capacitor (C₃), first to third diode (D₆, D₇, D₅) and capacitor (C₄) is present and supply common buffer capacitors (C₁, C₂).
 24. Circuit arrangement according to claim 23, characterised in that the individual input stages are connected in parallel and can be switched on as a function of the power to be transmitted instantaneously.
 25. Circuit arrangement according to claim 23, characterised in that the plurality of input stages can be used independently of each other and are supplied at the same time from different sources, such as solar generators, fuel cells or batteries. 